Lead verification engineer verifying digital RTL and reusable components for Cadence’s high-performance physical IP. Driving coverage closure, test plans, and verification flows.
Responsibilities
Verify digital RTL
Develop reusable verification components and environments
Contribute to verification flow development
Develop and execute test plans
Drive functional coverage closure and code coverage closure
Communicate project development progress and status with technical staff
Collaborate with design, verification, project management, and digital and analog design teams across worldwide geographies
Work as part of a small and focused engineering team
Travel as required by the job function
Requirements
Bachelor of Science in Electrical (EE)/Computer Engineering (CPE) or Computer Science (CSC)
Understanding of verification architecture and methodologies
Understanding of Metric Driven Verification
Understanding of Universal Verification Methodologies
Understanding of the identification, planning and creation of functional coverage and checks
Understanding of SystemVerilog Assertions (SVAs)
Understanding of digital design flow
Able to work independently and complete assigned tasks within project timelines
Able to work as part of a small, focused engineering team and collaborate with design, verification, project management, and digital and analog design teams
Willing to work full time in the Montreal, Quebec, Canada office
Willing to travel as required, approximately 5% or less
Capable de communiquer en anglais
Benefits
paid vacation and holidays
leave of absence programs
Registered Retirement Savings Plan (RRSP)
Tax Free Savings (TFSA) plan for post-tax investment savings
Employee Stock Purchase Plan
group health coverage including dental, vision and Emotional Wellbeing Support (EAP) benefits
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