Co - op engineer validating SiTime’s MEMS timing ASIC devices through PCB debugging, lab characterization, and Python test automation. Supporting pre - silicon drivers and production - readiness verification.
About the role
- Co-op ASIC Digital Verification Engineer contributing to verification of SiTime’s mixed-signal PLL integrated circuits. Learning testbench and test-case development within the ASIC verification team.
Responsibilities
- Gain exposure to ASIC verification
- Contribute to verification efforts for ongoing projects
- Learn about the verification environment, test bench, and test-case writing
- Complete several defined tasks contributing to the verification team
- Work with diverse local and remote design and verification team members
- Develop knowledge and gain experience in ASIC verification for mixed-signal PLL integrated circuits
Requirements
- Good academic standing
- Object oriented coding skills
- Strong problem-solving skills
- English proficiency, including the ability to effectively communicate, collaborate, and perform job responsibilities in a professional business environment
- Knowledge of Verilog, SystemVerilog and UVM are assets
- Knowledge of scripting languages such as Python and Tcl is an asset
- Ability to work under minimal supervision
- Good communication skills
- Co-op/Intern position starting in January 2027
Benefits
- Temporary full-time position, 40 hours/week, for 16 weeks
- Quarterly bonus tied to the achievement of innovation goals
- Equity grants
- Equal Opportunity Employer
- E-Verify program participation
Job title
Job type
Experience level
Salary
Not specified
Degree requirement
No Education Requirement
Tech skills
Location requirements
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