About the role

Senior Staff Analog Design Engineer providing technical leadership in developing advanced clock and timing products. Leading circuit design and collaborating in a fast-paced environment at SiTime.

Responsibilities

Define, design, and develop innovative circuits for high-performance timing products
Mentor, lead, and guide junior designers
Collaborate effectively with remote engineering teams
Support prototype testing, debugging, and lab characterization
Provide technical support across the full product development cycle through production release

Master’s or PhD degree in Electrical Engineering
10+ years of relevant experience in analog/mixed-signal CMOS design
Strong knowledge of integrated circuit design, device physics, and process technology
Experience designing PLLs or related building blocks, including VCOs, phase detectors, charge pumps, and similar circuits
Deep understanding of transistor behavior, circuit noise theory, and phase noise concepts
Proficiency with the Cadence analog/mixed-signal simulation toolset
Familiarity with analog/mixed-signal design flow, simulation methods, design rules, post-layout verification
Experience with analog behavioral modeling using SystemVerilog, Verilog-A, or AMS
Hands-on experience with lab testing and characterization

quarterly bonus tied to the achievement of innovation goals
equity grants, providing a meaningful opportunity to share in the company’s future growth and success