About the role

Analog IC Design Architect developing CMOS analog/mixed-signal SerDes circuits at Cadence. Designing long-reach links through simulation, verification, and lab testing.

Responsibilities

Design and develop analog/mixed-signal IC circuit blocks from initial concept and specification through final verification of conformance to customer specifications
Contribute to the design of long-reach SerDes
Perform circuit simulation and post-layout verification using CAD tools
Support lab testing and design activities at ≥16Gbps and in ≤16nm technologies

Minimum of 10 years of experience in the development of CMOS SerDes or high-speed I/O IC
Thorough understanding of jitter and signal equalization techniques
Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
Excellent problem-solving skills, good communication skills, and ability to work cooperatively in a team environment
Working knowledge of common SerDes standards and their electrical requirements is a plus
Proficiency in CAD tools for circuit simulation and post-layout verification
Proficiency with layout entry is a plus
Cadence tool experience
Lab test experience
Design experience at ≥16Gbps and in ≤16nm technologies
MS or PhD in EE

We welcome applications from candidates with disabilities and in equity seeking groups
Accessibility support during the application and interview process