Senior analog/mixed-signal IC Designer developing high-speed CMOS circuits for Cisco Acacia optical transceivers. Leading complex chip blocks, ASIC integration, validation and design methodology.
Responsibilities
Architect, design, lay out, measure and productize ultra-deep-submicron CMOS products
Develop high-speed and high-accuracy analog designs for optical communications products
Lead efforts for a large block on a complex chip
Mentor team members and track deliverables
Participate in peer reviews of complex IC designs
Provide design methodology from conception through production
Collaborate with packaging and hardware design teams to meet signal- and power-integrity specifications
Collaborate with mixed-signal engineers to optimize designs for ASIC integration
Interact with digital/DSP, system, package and module design groups
Requirements
BSEE degree with 12+ years of experience, or an MS degree with 8+ years of experience, or a PhD with 5+ years of experience
Experience in design, simulation and measurement of high-speed ICs in at least 3 listed areas
Experience with high-speed serial links using serializers, deserializers and data converters
Experience modeling requirements for system link simulations
Experience with high-performance output drivers
Experience with high-performance phase-locked loops
Experience with efficient clock transmission/propagation
Experience with op-amps and programmable gain amplifiers
Experience with equalization techniques
Preferred: experience with electrical transceiver applications, including backplane and cable communications
Preferred: experience in FinFET and GAA technologies
Preferred: high-frequency layout experience, including floorplanning, power/ground and digital/analog signal routing, inductors, transformers and transmission lines
Preferred: design-for-manufacturability experience, including PVT characterization, electromigration, self-heating and IR-drop analysis
Preferred: laboratory validation experience, including ESD practices/methodology and test setup construction
Preferred: experience with Cadence Virtuoso, Spectre/APS/SpectreX, Virtuoso and Calibre, EMX, AMS mixed-signal simulations and Matlab
Benefits
Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies
Sales incentive compensation for employees on sales plans, subject to applicable Cisco plans
Cisco careers site offers additional benefits and perks
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