Lead functional logic verification for integrated SoC design ensuring specifications are met. Collaborate with cross-functional teams to enhance verification and mentor technical leaders.
Responsibilities
Performs functional logic verification of an integrated SoC to ensure design will meet specifications.
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintains and improves existing functional verification infrastructure and methodology.
Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.
As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry.
Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values.
Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market.
Requirements
Experience leading two or more SOC or complex Compute Sub system level verification based on x86 or latest ARM cores
Experience in debugging the issues in the SOC like tracking the transactions in waveforms, Processor Core booting etc
Experience in building Testbenches for SOC including the latest verification tools and methodologies from EDA vendors
Good understanding of Cache Coherency, memory management and Interrupt flows
Good Post silicon bring up debug experience
Good Scripting , Understanding of various Core boot, Good Understanding on emulation bring up
Benefits
Intel is committed to a culture of accessibility.
Intel provides accommodations to applicants and employees with disabilities.
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