Propulsion Systems Engineer supporting aerospace engineering activities related to systems integration and problem - solving. Participating in technical studies and ensuring adherence to project milestones in Montreal.
About the role
- Senior Verification Engineer in ASIC design verification at Intel Corporation. Leading verification efforts and collaborating across teams to ensure quality in semiconductor product development.
Responsibilities
- Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs.
- Ensure meeting the required coverage levels and conform to microarchitecture specifications.
- Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs.
- Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
- Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
- Collaborate Across Teams: Work closely with SoC architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
- Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies. Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
- Lead and mentor others: inspire and guide junior engineers, fostering their growth and development. Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives.
Requirements
- Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree.
- 5+ years of experience in ASIC/FPGA design verification
- Experience in developing UVM and/or Formal based verification architectures and methodologies.
- Experience with industry standard protocols such as AMBA AXI/AXI-S/CHI/APB and Low-speed communication protocols such as UART, SPI or I2C/I3C
- Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
- Experience with coverage-driven verification, constrained-random testing and strong debugging skills.
- Experience with scripting languages such as Python, TCL, and Shell scripting.
- Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ yrs. of experience.
- Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain.
- Collaborative, able to communicate well with counterparts and stakeholders.
- Strong written and verbal communication skills.
- Strong analytical ability and problem-solving skills.
- Experience in defining testbench architecture, constrained random verification methodologies.
- Experience in processor-based verification using C/C++ with UVM-based verification environments.
- Define and execute validation of IPs and/or SOC from spec to tape-in including setting verification strategy, creating test bench and components, defining test plan, writing tests, debugging, coverage and analysis.
- Low power experience (e.g., UPF).
- Experience in CXS stream, DDR, PCIe and/or Ethernet, UCIe protocols.
- Experience in EDA tools and reusable testbench for subsystem and SoC that deploys 3rd party VIPs.
- Experience with formal verification techniques and tools is an asset.
Benefits
- Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities.
Job title
Job type
Experience level
Salary
Degree requirement
Tech skills
Location requirements
Report this job
Found something wrong with the page? Please let us know by submitting a report below.
Structural Engineer involved in designing and inspecting various structures. Collaborating with multidisciplinary teams to ensure project quality and performance standards.
LP
Performance Test Engineer (Dynatrace & LoadRunner)
LinkedIn Recruiter Post
Performance Test Engineer (Dynatrace & LoadRunner) - Hybrid, Toronto. Contract role requiring 7 - 9 years of experience.
Technical Services Engineer developing technical submetering solutions for clients in mixed - use communities. Collaborating with property developers and internal teams to ensure accurate utility billing.
Electrical & Instrumentation Engineer overseeing installation and troubleshooting of electrical systems for mining projects. Collaborating with teams to ensure compliance with design and safety standards.
Quality Performance Senior Engineer at City National driving quality initiatives for scalable applications. Collaborating with teams to enhance system architecture and performance metrics.
Senior Release Train Engineer leading large - scale Agile delivery for Manulife's Insurance Technology team. Aligning cross - functional teams to drive meaningful business outcomes while fostering collaboration and continuous improvement.
In - Building RF Engineer at TELUS designing and optimizing indoor distributed antenna systems. Leading innovation through automation and collaboration with cross - functional teams.
Staff Platform Engineer developing internal systems and automations for Shakepay's engineering teams. Enhancing productivity and technical architecture while collaborating across teams.
EX
CPI position in building electrical engineering at EXP. Involvement in electrical design projects for various sectors with collaborative and innovative work environment.