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About the role
- Senior Verification Engineer in ASIC design verification at Intel Corporation. Leading verification efforts and collaborating across teams to ensure quality in semiconductor product development.
Responsibilities
- Define Project Specific Verification Strategy: Defines and implement scalable and reusable verification plans, test benches, and the verification environments for blocks, subsystems, and SoCs.
- Ensure meeting the required coverage levels and conform to microarchitecture specifications.
- Lead Verification Execution: Create detailed test plans and drives technical reviews with design and architecture teams to validate these plans and proofs.
- Executes verification plan: Implement and run block/subsystem/cluster/soc simulation models to verify the design, analyze power and performance, and identify bugs.
- Investigate and Resolve Bugs: Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
- Collaborate Across Teams: Work closely with SoC architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
- Enhance Future Verification Methodologies: Continuously improves existing functional verification infrastructure and methodologies. Absorbs learnings: From post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.
- Lead and mentor others: inspire and guide junior engineers, fostering their growth and development. Your expertise will be instrumental in cultivating a collaborative and innovative environment where every team member thrives.
Requirements
- Bachelor's degree in electrical engineering, computer engineering, computer science, or in other relevant STEM related degree.
- 5+ years of experience in ASIC/FPGA design verification
- Experience in developing UVM and/or Formal based verification architectures and methodologies.
- Experience with industry standard protocols such as AMBA AXI/AXI-S/CHI/APB and Low-speed communication protocols such as UART, SPI or I2C/I3C
- Hands-on experience with simulators (Synopsys VCS, Cadence Xcelium, or equivalent).
- Experience with coverage-driven verification, constrained-random testing and strong debugging skills.
- Experience with scripting languages such as Python, TCL, and Shell scripting.
- Graduate/post-graduate degree in electrical engineering, computer engineering, computer science, or any STEM related degree with overall 8+ yrs. of experience.
- Skilled in various validation concepts and debug techniques relevant to ASIC/FPGA domain.
- Collaborative, able to communicate well with counterparts and stakeholders.
- Strong written and verbal communication skills.
- Strong analytical ability and problem-solving skills.
- Experience in defining testbench architecture, constrained random verification methodologies.
- Experience in processor-based verification using C/C++ with UVM-based verification environments.
- Define and execute validation of IPs and/or SOC from spec to tape-in including setting verification strategy, creating test bench and components, defining test plan, writing tests, debugging, coverage and analysis.
- Low power experience (e.g., UPF).
- Experience in CXS stream, DDR, PCIe and/or Ethernet, UCIe protocols.
- Experience in EDA tools and reusable testbench for subsystem and SoC that deploys 3rd party VIPs.
- Experience with formal verification techniques and tools is an asset.
Benefits
- Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities.
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