Principal Analog Mixed-Signal Design Engineer – Optical

Posted 2 days ago

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About the role

  • Principal analog mixed-signal engineer designing high-speed optical TIAs and broadband circuits at Marvell. Supporting validation, qualification, mass production, and customer semiconductor applications.

Responsibilities

  • Design and validate FET and BiCMOS circuits for high-speed broadband ICs
  • Design active circuits
  • Design leading-edge, multi-tens-of-GHz transimpedance amplifiers using SiGe BiCMOS and advanced CMOS FinFET technologies
  • Develop transmission-line and other millimeter-wave structures
  • Design high-performance broadband analog circuits for optical front-end receivers
  • Design analog circuits including linear regulators, AGC loops, current/voltage sensors, and bandgaps
  • Work with functional groups on post-silicon validation, qualification, transition to mass production, and customer support
  • Contribute to optical interface chips and high-performance equalizers for coherent long-haul, metro, and PAM4 data-center systems

Requirements

  • Bachelor’s degree in Electrical Engineering with 10+ years of industry experience OR Master’s or PhD degree in Electrical Engineering with 7+ years of industry experience in high-performance RF/Analog Receiver/TIA design
  • Proven experience in high-performance receiver design, including chip tape-out and lab evaluation
  • Experience using EDA CAD tools
  • Experience performing analog custom layout
  • Experience measuring IC performance and debugging designs to correlate simulations to measurements
  • Deep understanding of transistor-level design, device physics, and control/feedback loop stability analysis
  • Package-system integration experience desired
  • Project experience using SiGe BiCMOS and FinFET CMOS technologies is a plus
  • Strong communication, presentation, and documentation skills
  • Experience overseeing and mentoring junior circuit designers is a plus
  • Experience as chip lead with success in silicon is a plus
  • Experience taking chips to mass production is a plus
  • Ability to translate chip-level specifications into architecture
  • Team player
  • Eligibility to access export-controlled information under applicable U.S. export control laws and regulations

Benefits

  • Bonus plan eligibility
  • Equity plans, including a new hire equity grant and annual equity refreshers
  • Competitive compensation and great benefits
  • Tools and resources to succeed
  • Opportunities to grow and develop
  • Inclusive, collaborative work environment

Job type

Full Time

Experience level

Lead

Salary

CA$164,000 - CA$218,700 per year

Degree requirement

Bachelor's Degree

Location requirements

OnsiteOttawaCanada

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