Junior/Intermediate FPGA Engineer developing FPGA - based systems for Kardium's groundbreaking medical devices. Collaborating within a technical team to enhance user outcomes and device performance in a hybrid work environment.
About the role
- Digital Verification Engineer developing mixed-signal Digital PLL ASICs for SiTime’s MEMS precision-timing products. Creating verification tests, debugging simulations, and driving coverage and verification closure.
Responsibilities
- Define and implement self-checking test cases based on functional requirements
- Contribute to verification infrastructure components
- Triage regressions
- Debug RTL and gate-level simulations
- Analyze coverage
- Work with other teams to resolve issues and achieve verification closure
- Participate in verification planning and continuous improvement of the verification environment
- Work with diverse design and verification team members, both local and remote
Requirements
- Understand standard specifications, functional specifications, and feature enhancements to create and execute detailed verification plans
- Knowledge of SystemVerilog and UVM environments for digital verification
- Experience with Synopsys and/or Cadence simulation tools
- Experience with SystemVerilog assertions
- Experience with functional coverage and code coverage
- Ability to work in a Unix/Linux operating system environment
- Fast learner able to work under minimal supervision
- Effective team player with good communication skills
Benefits
- Annual base salary of CAD 75,770 - CAD 104,190
- Quarterly bonus tied to the achievement of innovation goals
- Equity grants
- Comprehensive and highly competitive compensation package
- Equal Opportunity Employer
- SiTime participates in the E-Verify program
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Experience level
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Degree requirement
No Education Requirement
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