About the role

Principal Analog/mixed-signal IC Developer designing high-speed ICs for optical communications products. Leading a dynamic IC Design group in advanced signal processing and photonic integration.

Responsibilities

collaborate with other Acacia mixed-signal engineers to provide an optimized design that will integrate into the DSP ASIC
lead the team in architect, design, layout, measure and productize ultra-deep sub-micron-based CMOS products
lead efforts for large block on complex chip, mentor team members and track deliverables
participate in peer review of complex IC designs and provide solid design methodology from conception to production
collaborate with packaging and hardware design team to ensure signal and power integrity specifications are met
accountable for developing high speed AMS circuits and best-in-class products that push the boundaries of what is possible
detail oriented, high energy and driven to solve difficult problems
participate in friendly and team-oriented collaboration approach, enjoy learning from colleagues and letting them learn from you.
committed to improving team effectiveness and welcoming feedback from team members.

Bachelors + 15 years of related experience, or Masters + 10 years of related experience, or PhD + 7 years of related experience
experience in the design, simulation, and measurement of high-speed ICs across at least three of the following areas: SerDes/serial links, output drivers, Phase Locked Loops (PLLs), clock distribution, Opamps/PGAs, or equalization techniques
direct experience as a leader of a team working on high performance circuits
preferred: experience with electrical transceiver applications including backplane and cable communications
preferred: experience in FinFET and GAA technologies
preferred: high-frequency layout experience including floorplanning (power/ground, digital/analog signal routing), passive components (inductors, transformers, and transmission lines)
preferred: experience in design for manufacturability including characterization over PVT, electromigration analysis, self-heating, and IR drop analysis
preferred: experience in laboratory validation including ESD practices/methodology and construction of test setups
preferred: experience in design software including Cadence (Virtuoso), Specture/APS/SpectreX, layout validation tools (Virtuoso and Calibre), EMX, mixed-signal simulations in AMS, and Matlab.

medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year
up to 80 hours of unused sick time carried forward from one calendar year to the next
Optional 10 paid days per full calendar year to volunteer
eligibility for annual bonuses