About the role

Developer building YosysHQ’s open-source EDA tools for synthesis or formal verification. Applying C++, Rust, Python, hardware design, and formal methods expertise.

Responsibilities

Contribute to YosysHQ’s synthesis or formal verification focus areas
Develop and maintain open-source EDA tools and software packages
Work on formal verification tools using C++, Rust, and Python
Implement hardware model checking and related formal methods
Develop synthesis functionality using C++ and RTL hardware design knowledge
Work on custom development of individual features and complete flows based on YosysHQ software components
Support and train users and developers working with the software
Independently take responsibility for assigned tasks and resolve challenges
Participate in team meetings typically held between 3pm and 6pm Vienna time (CET/CEST)

Comfortable with C++ or Rust for formal verification; willingness to learn the other languages and Python
Familiarity with implementation of hardware model checking, or background in verification/formal methods such as SAT/SMT solving, automated/interactive theorem proving, programming language theory, or automata theory
Some contact with RTL hardware design for formal verification
Comfortable with C++ for synthesis
Some experience with RTL hardware design, ideally for ASIC
Transferable experience building software for engineering or science applications, implementing algorithms from scientific literature, or working on a compiler
Experience becoming familiar with a large pre-existing project
Ability to take responsibility, work independently, and address challenges without extensive supervision
Must not live in a country subject to sanctions or export restrictions, or be banned from performing work for the US government
CV and brief cover letter required for application