About the role

Design Verification Engineer with 7-13 years experience in SystemVerilog & UVM for verifying display IPs in graphics cards. Onsite role in Markham, ON.

Responsibilities

Perform functional verification of display IPs used in graphics processing units (GPUs). Develop and execute IP, subsystem (SS), and end-to-end test plans. Design and implement testbenches using SystemVerilog and UVM. Create reusable verification components, environments, and test cases. Perform debugging, root cause analysis, and issue resolution. Collaborate with design and architecture teams to understand specifications and ensure coverage. Ensure thorough coverage (code & functional) and regression testing. Participate in verification planning, reviews, and documentation.

7–13 years of experience in Design Verification. Strong expertise in: SystemVerilog (SV) UVM (Universal Verification Methodology) Hands-on experience with DV flow including testbench development, simulation, and debugging. Experience in IP/Subsystem level and end-to-end verification. Solid understanding of digital design fundamentals. Experience with display IP verification or graphics-related domains is highly preferred. Strong debugging and analytical skills.