Intermediate Municipal Engineer managing civil engineering projects at GEMTEC. Collaborating with teams and ensuring project delivery within budget and scope.
About the role
- STA Engineer at eInfochips performing timing validation and quality checks on incoming IPs with Siemens tools for robust semiconductor design.
Responsibilities
- Timing expert preferably w/ Siemens Fractal/Crosscheck tool experience for quality checks of incoming IPs
- Familiarity with various .lib views and preferably Siemens Fractal/Crosscheck tool configuration experience
- Incoming IP view comparisons with previously released views using internal flow and configuring the crosscheck tool to filter out real violations and flag QA issues.
- CrossFire (Now Solido CrossCheck): A tool used for rigorous validation of Liberty files (.lib), Verilog, GDSII, and SPICE models.
- IPdelta: A tool designed to characterize and compare differences between versions of IP, helping to identify changes in timing or power characteristics between two revisions.
- Library Validation: Ensures that the timing, power, and noise characteristics (Liberty format) are accurate, consistent, and logical.
- Process Design Kit (PDK) & IP Check: Validates third-party or internal IP, including standard cell libraries and I/O.
- Format Consistency: Ensures compatibility and correctness across different EDA tool formats.
Requirements
- Experience: 5+ Years
- Timing expert preferably w/ Siemens Fractal/Crosscheck tool experience for quality checks of incoming IPs
- Familiarity with various .lib views and preferably Siemens Fractal/Crosscheck tool configuration experience
- Incoming IP view comparisons with previously released views using internal flow and configuring the crosscheck tool to filter out real violations and flag QA issues.
- CrossFire (Now Solido CrossCheck): A tool used for rigorous validation of Liberty files (.lib), Verilog, GDSII, and SPICE models.
- IPdelta: A tool designed to characterize and compare differences between versions of IP, helping to identify changes in timing or power characteristics between two revisions.
- Library Validation: Ensures that the timing, power, and noise characteristics (Liberty format) are accurate, consistent, and logical.
- Process Design Kit (PDK) & IP Check: Validates third-party or internal IP, including standard cell libraries and I/O.
- Format Consistency: Ensures compatibility and correctness across different EDA tool formats.
Benefits
- Medical, Dental, Vision Insurance
- 401k, With Matching Contributions
- Short-Term/Long-Term Disability Insurance
- Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
- Paid Time Off (including sick, holiday, vacation, etc.)
- Tuition Reimbursement
- Growth Opportunities
- And more!
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