About the role

Senior Digital Verification Engineer at Ciena focusing on implementing innovative strategies for validating Forward Error Correction IP subsystems. Collaborating with design engineers to ensure functional integrity.

Responsibilities

Read and understand the FEC architecture and functional requirements specification document(s) and communicate and collaborate with FEC designers, DSP modelers, FEC verifiers, systems engineers and architects
Develop verification, functional coverage and formal verification test plans
Thoroughly validate one or more architectural FEC functional blocks using a combination of simulation, formal, and coverage methods
Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and C++
Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function's designer
Provide status updates on verification progress on a regular basis and communicate risks as needed
Mentor and supervise junior verification engineers

10+ years of experience in verification
Minimum Bachelor's degree in Electrical, Computer or Software Engineering
Significant experience in using C/C++, System Verilog, UVM, SVA, and simulators from major vendors
Proven ability to determine comprehensive digital verification and coverage strategies
Proven ability to foster a culture of innovation and continuous improvement within the team via demonstrated leadership and communication capabilities
Strong decision-making skills with the ability to analyze complex situations, evaluate options and implement effective solutions to meet deliverables

medical, dental, and vision plans
participation in 401(K) (USA) & DCPP (Canada) with company matching
Employee Stock Purchase Program (ESPP)
Employee Assistance Program (EAP)
company-paid holidays
paid sick leave
vacation time
comply with all applicable laws regarding Paid Family Leave and other leaves of absence