Staff Physical Design Engineer driving physical implementation of EnCharge AI’s advanced AI hardware chips. Optimizing timing, power, and area from netlist through foundry tapeout.
Responsibilities
Drive block-level and top-level physical design, including floor-planning, placement, clock tree synthesis (CTS), and routing.
Achieve aggressive timing, power, and area (PPA) targets through advanced timing closure techniques.
Perform power grid verification and manage electromigration and IR drop (EM/IR) analysis and resolution.
Develop and maintain automation scripts (Tcl/Python) to streamline design flows and methodologies.
Collaborate with physical verification and foundry teams to ensure design rule compliance and successful tapeout execution.
Translate complex microarchitectures into high-performance, power-efficient silicon.
Own implementation from netlist to successful foundry tapeout.
Requirements
Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
10–15 years of dedicated experience in physical design.
Strong understanding of EDA implementation flows with extensive experience using Cadence design tools.
Deep understanding of static timing analysis (STA) concepts and advanced timing closure methodologies.
Demonstrated success in top-level and block-level physical design, with hierarchical floorplanning expertise a strong plus.
Proficiency in low-power design techniques, debugging, and EM/IR check resolution/power grid verification.
Strong scripting skills in Tcl or Python for design flow automation.
Solid understanding of advanced process nodes and physical verification requirements associated with routing.
Experience with physical design methodology, flow setup, and advanced flow evaluations.
Prior experience with PDK management or foundry tapeout processes is highly desirable.
Equal employment opportunity employer in the United States.
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