Mechanical Engineer designing district energy and low - carbon thermal systems for KWL, a Canadian infrastructure consulting firm. Managing technical scopes, client relationships, proposals, and project delivery across Ontario.
About the role
- Senior Manager leading digital circuit design and multi-site engineering teams for Microchip’s communications semiconductor solutions. Delivering networking, connectivity, and edge-compute devices from R&D through production.
Responsibilities
- Provide technical leadership for communication semiconductor devices or subsystems
- Oversee design and implementation of digital circuits at block or top level
- Lead large, multi-site engineering teams delivering highly integrated silicon solutions
- Drive project completion through architects, domain experts and empowered team leaders
- Coordinate with cross-functional teams to deliver project goals
- Manage and mentor engineers, including guidance, support and professional development
- Expand team knowledge across technical expertise in technologies, flows and standards
- Guide enhancement of internal proprietary flows and practices
- Foster a collaborative and innovative work environment
- Collaborate with Software, Validation and Production Engineers to deliver production-worthy devices
- Potentially manage direct reports and contractors
- Enhance CBU technical capabilities through mentorship, coaching and recruitment
Requirements
- Bachelor’s or Master’s Degree in Electrical Engineering or Computer Engineering
- 12+ years related experience
- Proven leadership skills, having previously led large or small teams
- Strong coaching and mentoring skills
- Ability to think both strategically and tactically
- Excellent analytical and debugging skills and the ability to proactively solve issues
- Proven ability to thrive on, learn and adapt to new methodologies and technologies
- Experience in designing, synthesizing or verifying Verilog or VHDL based designs for silicon, on FPGA or other platforms
- Excellent verbal and written communication skills in English
- Experience designing System-on-a-Chip (SOC) devices (an asset)
- Familiarity with communication protocols such as Ethernet, OTN, ASA and others (an asset)
- Experience with Synopsys or Cadence tool flows for synthesis, verification or STA (an asset)
- Experience with 28nm and smaller silicon process technologies (an asset)
- Travel availability of 0%-25%
Benefits
- Competitive base pay
- Restricted stock units
- Quarterly bonus payments
- Health benefits beginning day one
- Retirement savings plans
- Industry leading IESPP program with a 6-month look back feature
- Employee development and Leadership Passage Programs
- Professional development opportunities
- Travel allowance/coverage implied by business travel requirements (0%-25%)
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