Package layout engineer developing high-speed semiconductor interconnects for Semtech’s semiconductor solutions. Designing advanced substrates, PCBs, and wafer-level layouts across 2D, 2.5D, and 3D IC technologies.
Responsibilities
Perform package design feasibility assessments for signal integrity experts with manufacturing and thermo-mechanical engineering teams.
Develop multi-layer substrate and carrier layouts for 2D, 2.5D, and 3D IC configurations.
Develop wafer-level interconnect layouts using wafer redistribution layers and wafer reconstruction technologies.
Contribute innovative high-speed designs across interconnect technologies.
Requirements
Bachelor’s degree in engineering, physics, or another discipline relevant to the position.
5 years of layout experience in high-speed package and/or advanced PCB technologies.
Solid knowledge of high-speed layout and electronic design.
Advanced knowledge of EDA layout tools.
Familiarity with PCB layout, as well as mechanical, thermal, and optical design.
Understanding of RF, analog, and digital circuits.
Ability to work in parallel with several cross-functional internal teams, while coordinating with local and international suppliers.
Excellent written and oral communication skills, and the ability to work well with other team members.
Ability to work independently with little supervision in a fast-paced environment.
Advanced knowledge of Cadence APD and Allegro preferred.
Knowledge of AI design acceleration features in EDA layout tools preferred.
Additional degrees or certifications in mechatronics, photonics, or electronics manufacturing preferred.
Familiarity with chip-on-board, wirebond, flip-chip, optical assembly, and high-speed connectors preferred.
Familiarity with JEDEC and IPC standards preferred.
Experience troubleshooting PCBs and systems preferred.
Ingénieure en génie routier concevant plans et devis pour routes, autoroutes et ponts chez Stantec. Contribuant aux études, estimations et suivis de travaux au Québec.
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